Tag Archive: VHDL


VHDL code for full adder


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Here is the VHDL code for FULL ADDER:

 

 

 

 

 

 

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY fulladd IS
PORT (    Cin, x, y        : IN     STD_LOGIC ;
s, Cout            : OUT     STD_LOGIC ) ;
END fulladd ;

ARCHITECTURE beh OF fulladd IS
BEGIN
s <= x XOR y XOR Cin ;
Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
END beh ;

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VHDL Code for 4 Bit Comparator


4 bit comparator

 

 

 

 

 

 

 

The vhdl coding for a 4 bit comparator is as follows:-

Its a behavioural type of modelling…..


LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
ENTITY compare IS
PORT ( A, B : IN SIGNED(3 DOWNTO 0) ;
AeqB, AgtB, AltB : OUT STD_LOGIC ) ;
END compare ;
ARCHITECTURE Behavior OF compare IS
BEGIN
AeqB <= ‘1’ WHEN A = B ELSE ‘0’ ;
AgtB <= ‘1’ WHEN A > B ELSE ‘0’ ;
AltB <= ‘1’ WHEN A < B ELSE ‘0’ ;
END Behavior ;