VHDL code for full adder

RELATED POSTS:

1.VHDL Code for 4 bit comparator

2.VHDL code for d flip flop

3.VHDL code for 2 to 4 binary decoder

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Here is the VHDL code for FULL ADDER:

 

 

 

 

 

 

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY fulladd IS
PORT (    Cin, x, y        : IN     STD_LOGIC ;
s, Cout            : OUT     STD_LOGIC ) ;
END fulladd ;

ARCHITECTURE beh OF fulladd IS
BEGIN
s <= x XOR y XOR Cin ;
Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
END beh ;

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VHDL code for D-Flip Flop

RELATED POSTS:

1.VHDL code for 2 to 4 binary decoder

2.VHDL code for 4 bit comparator

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Here is the VHDL coding of the d-flip flop :

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY flipflop IS
PORT (     D, Resetn, Clock     : IN     STD_LOGIC ;
Q                     : OUT     STD_LOGIC) ;
END flipflop ;

ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock’EVENT AND Clock = ‘1’ ;
IF Resetn = ‘0’ THEN
Q <= ‘0’ ;
ELSE
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;

VHDL code of a 2 to 4 binary decoder

 

 

 

 

 

 

 

Well below is the VHDL coding of a 2 to 4 binary decoder:

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;
END dec2to4 ;
ARCHITECTURE Behavior OF dec2to4 IS
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
Enw <= En & w ;
WITH Enw SELECT
y <= “1000” WHEN “100”,
“0100” WHEN “101”,
“0010” WHEN “110”,
“0001” WHEN “111”,
“0000” WHEN OTHERS ;
END Behavior ;

VHDL Code for 4 Bit Comparator

 

 

 

 

 

 

 

The vhdl coding for a 4 bit comparator is as follows:-

Its a behavioural type of modelling…..

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
ENTITY compare IS
PORT ( A, B : IN SIGNED(3 DOWNTO 0) ;
AeqB, AgtB, AltB : OUT STD_LOGIC ) ;
END compare ;
ARCHITECTURE Behavior OF compare IS
BEGIN
AeqB <= ‘1’ WHEN A = B ELSE ‘0’ ;
AgtB <= ‘1’ WHEN A > B ELSE ‘0’ ;
AltB <= ‘1’ WHEN A < B ELSE ‘0’ ;
END Behavior ;