4 bit comparator

 

 

 

 

 

 

 

The vhdl coding for a 4 bit comparator is as follows:-

Its a behavioural type of modelling…..


LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;
ENTITY compare IS
PORT ( A, B : IN SIGNED(3 DOWNTO 0) ;
AeqB, AgtB, AltB : OUT STD_LOGIC ) ;
END compare ;
ARCHITECTURE Behavior OF compare IS
BEGIN
AeqB <= ’1′ WHEN A = B ELSE ’0′ ;
AgtB <= ’1′ WHEN A > B ELSE ’0′ ;
AltB <= ’1′ WHEN A < B ELSE ’0′ ;
END Behavior ;

 

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